A Formal Framework for Maximum Error Estimation in Approximate Logic Synthesis

Approximate logic synthesis techniques have become popular in error-resilient systems, where accuracy requirements can be traded for improved energy efficiency. Many of these operate on a circuit by substituting or removing some its portions under predefined error constraint; however, the research systematic methods to determine induced such transformations is still at an early stage. We propose herein generic framework modeling maximum circuit, called partition and propagate, which fundamental preliminary step ALS. This based partitioning propagation among subcircuits. provide sound, complete formal description framework, we illustrate how two state-of-the-art algorithms subsumed it. Moreover, novel gate-level error-modeling algorithm, able identify whole range possible errors given approximate transformation. compare three strategies efficiency new error-propagation methodology, accurate bounds and, hence, guide ALS more valuable solutions.